
/*
 * PL110/PL111 CLCD Controller Register addresses
 */
#define CLCD_TIM0 0x00000000
#define CLCD_TIM1 0x00000004
#define CLCD_TIM2 0x00000008
#define CLCD_TIM3 0x0000000c
#define CLCD_UBAS 0x00000010
#define CLCD_LBAS 0x00000014

#define CLCD_PL110_IENB 0x00000018
#define CLCD_PL110_CNTL 0x0000001c
#define CLCD_PL110_STAT 0x00000020
#define CLCD_PL110_INTR 0x00000024
#define CLCD_PL110_UCUR 0x00000028
#define CLCD_PL110_LCUR 0x0000002C

#define CLCD_PL111_CNTL 0x00000018
#define CLCD_PL111_IENB 0x0000001c
#define CLCD_PL111_RIS 0x00000020
#define CLCD_PL111_MIS 0x00000024
#define CLCD_PL111_ICR 0x00000028
#define CLCD_PL111_UCUR 0x0000002c
#define CLCD_PL111_LCUR 0x00000030

#define CLCD_PALL 0x00000200
#define CLCD_PALETTE 0x00000200

#define TIM2_PCD_LO_MASK GENMASK(4, 0)
#define TIM2_PCD_LO_BITS 5
#define TIM2_CLKSEL (1 << 5)
#define TIM2_ACB_MASK GENMASK(10, 6)
#define TIM2_IVS (1 << 11)
#define TIM2_IHS (1 << 12)
#define TIM2_IPC (1 << 13)
#define TIM2_IOE (1 << 14)
#define TIM2_BCD (1 << 26)
#define TIM2_PCD_HI_MASK GENMASK(31, 27)
#define TIM2_PCD_HI_BITS 5
#define TIM2_PCD_HI_SHIFT 27

#define CNTL_LCDEN (1 << 0)
#define CNTL_LCDBPP1 (0 << 1)
#define CNTL_LCDBPP2 (1 << 1)
#define CNTL_LCDBPP4 (2 << 1)
#define CNTL_LCDBPP8 (3 << 1)
#define CNTL_LCDBPP16 (4 << 1)
#define CNTL_LCDBPP16_565 (6 << 1)
#define CNTL_LCDBPP16_444 (7 << 1)
#define CNTL_LCDBPP24 (5 << 1)
#define CNTL_LCDBW (1 << 4)
#define CNTL_LCDTFT (1 << 5)
#define CNTL_LCDMONO8 (1 << 6)
#define CNTL_LCDDUAL (1 << 7)
#define CNTL_BGR (1 << 8)
#define CNTL_BEBO (1 << 9)
#define CNTL_BEPO (1 << 10)
#define CNTL_LCDPWR (1 << 11)
#define CNTL_LCDVCOMP(x) ((x) << 12)
#define CNTL_LDMAFIFOTIME (1 << 15)
#define CNTL_WATERMARK (1 << 16)



#include "typedef.h"
#include "astralapi.h"

#define REG(name) *((volatile unsigned*) (base + name))


static int pl111_read(AstralDevice dev, char *buff, int buff_size, int *bytes_read)
{
    return 0;
}

static int pl111_write(AstralDevice dev, const char *buff, int buff_size, int *bytes_write)
{
    AstralDevice d = CAST_AS(AstralDevice, dev);
    void *base = d->vbase;

    REG(CLCD_UBAS) = CAST_AS(unsigned, buff);
    return 0;
}

static int pl111_open(AstralDevice dev, object arg)
{
    AstralDevice d = CAST_AS(AstralDevice, dev);
    void *base = d->vbase;

    // vga 640x480
    REG(CLCD_TIM0) = 0x3F1F3F9C;
    REG(CLCD_TIM1) = 0x090B616F;
    REG(CLCD_TIM2) = 0x067F1800;
    // svga 800x800
    REG(CLCD_TIM0) = 0X1313A4C4;
    REG(CLCD_TIM1) = 0x0505F6F7;
    REG(CLCD_TIM2) = 0x071F1800;

    REG(CLCD_UBAS) = CAST_AS(unsigned, 0x0);
    REG(CLCD_PL111_CNTL) = CNTL_LCDEN | CNTL_LCDPWR | CNTL_LCDTFT | CNTL_LCDBPP24;

    return 0;
}

static int pl111_close(AstralDevice dev, object arg)
{
    return 0;
}




static struct AstralDriver pl111_driver = {
    .dwrite = pl111_write,
    .dread = pl111_read,
    .dopen = pl111_open,
    .dclose = pl111_close,
    .description = "pl111 lcd driver"};

static void pl111_register(object arg)
{
    boolean status = register_driver(MIDv4(96, 1, 0, 2), &pl111_driver);
    kprint("register for %s done, status %d\n",
           pl111_driver.description,
           status);
}

STATIC_REGISTER_DRIVER(pl111_register)